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d a t a sh eet product speci?cation supersedes data of 2000 nov 14 2002 oct 25 integrated circuits tda8787a 10-bit, 3.0 v, up to 18 msps analog-to-digital interface for ccd cameras
2002 oct 25 2 philips semiconductors product speci?cation 10-bit, 3.0 v, up to 18 msps analog-to-digital interface for ccd cameras tda8787a features correlated double sampling (cds), programmable gain amplifier (pga), 10-bit analog-to-digital converter (adc) and reference regulator included fully programmable via a 3-wire serial interface sampling frequency up to 18 mhz pga gain range of 36 db (in steps of 0.1 db) low power consumption of only 170 mw at 2.7 v power consumption in standby mode of 4.5 mw (typical value) 3.0 v operation; 2.5 to 3.6 v operation for the digital outputs active control pulses polarity selectable via serial interface 8-bit dac included for analog settings ttl compatible inputs, cmos compatible outputs. applications low-power, low-voltage ccd camera systems. general description the tda8787a is a 10-bit analog-to-digital interface for ccd cameras. the device includes a correlated double sampling circuit, a pga, clamp loops and a low-power 10-bit adc, together with its reference voltage regulator. the pga gain and the adc input clamp level are controlled via the serial interface. an additional dac is provided for additional system controls. its output voltage range is 1.0 v peak-to-peak which is available at pin ofdout. ordering information type number package name description version tda8787ahl lqfp48 plastic low pro?le quad ?at package; 48 leads; body 7 7 1.4 mm sot313-2
2002 oct 25 3 philips semiconductors product speci?cation 10-bit, 3.0 v, up to 18 msps analog-to-digital interface for ccd cameras tda8787a quick reference data symbol parameter conditions min. typ. max. unit v cca analog supply voltage 2.7 3.0 3.6 v v ccd digital supply voltage 2.7 3.0 3.6 v v cco digital outputs stages supply voltage 2.5 2.6 3.6 v i cca analog supply current all clamps active; f pix = 18 mhz - 50 60 ma i ccd digital supply current f pix =18mhz - 13 17 ma i cco digital outputs supply current f pix = 18 mhz; c l = 20 pf; input ramp response time is 800 m s - 12ma adc res adc resolution - 10 - bits v i(cds)(p-p) cds input amplitude (video signal) (peak-to-peak value) v cc = 2.85 v 650 -- mv v cc 3 3.0 v 800 -- mv f pix(max) maximum pixel frequency 18 -- mhz f pix(min) minimum pixel frequency 2 -- mhz dr pga pga dynamic range - 36 - db n tot(rms) total noise (rms value) at cds input to adc output pga code = 0; see fig.8 - 0.15 - lsb v n(i)(eq)(rms) equivalent input noise voltage (rms value) pga code = 383 - 70 -m v p tot total power consumption v cca =v ccd =v cco =3v - 190 - mw v cca =v ccd =v cco = 2.7 v - 170 - mw
2002 oct 25 4 philips semiconductors product speci?cation 10-bit, 3.0 v, up to 18 msps analog-to-digital interface for ccd cameras tda8787a this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... block diagram d book, full pagewidth fce330 10-bit adc regulator cds clock generator blanking output buffer 26 27 28 29 30 31 32 33 34 35 36 37 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ognd 25 v cco 44 dclpc 38 v ccd2 39 dgnd2 19 v ccd1 20 dgnd1 41 agnd3 42 v cca3 8 cpcds2 7 cpcds1 4 in 5 agnd1 9 ofdout 6 v cca1 oe 11 blk 40 clk 43 agnd5 17 agnd2 2 dgnd3 1 v ccd3 18 v cca2 12 clpdm 13 clpob 47 shp shifter shift correlated double sampling 7-bit register 9-bit register 8-bit register 46 45 opga opgac 16 15 14 3 test1 agnd4 test2 test3 48 shd serial interface 21 22 23 sen sclk sdata 24 vsync 10 stdby pga dac input clamp v ref ofd dac latch clamp tda8787ahl fig.1 block diagram.
2002 oct 25 5 philips semiconductors product speci?cation 10-bit, 3.0 v, up to 18 msps analog-to-digital interface for ccd cameras tda8787a pinning symbol pin description v ccd3 1 digital supply voltage 3 dgnd3 2 digital ground 3 agnd4 3 analog ground 4 in 4 input signal from ccd agnd1 5 analog ground 1 v cca1 6 analog supply voltage 1 cpcds1 7 clamp storage capacitor 1 cpcds2 8 clamp storage capacitor 2 ofdout 9 analog output of the additional 8-bit control dac stdby 10 standby mode control input (low: tda8787a active; high: tda8787a standby) blk 11 blanking control input clpdm 12 clamp pulse input at dummy pixel (should be connected to ground) clpob 13 clamp pulse input for optical black test1 14 test pin input 1 (should be connected to agnd2) test2 15 test pin input 2 (should be connected to agnd2) test3 16 test pin input 3 (should be connected to agnd2) agnd2 17 analog ground 2 v cca2 18 analog supply voltage 2 v ccd1 19 digital supply voltage 1 dgnd1 20 digital ground 1 sdata 21 serial data input for serial interface control sclk 22 serial clock input for serial interface control sen 23 strobe pin for serial interface control vsync 24 vertical sync pulse input v cco 25 output stages supply voltage ognd 26 digital output ground d0 27 adc digital output 0 (lsb) d1 28 adc digital output 1 d2 29 adc digital output 2 d3 30 adc digital output 3 d4 31 adc digital output 4 d5 32 adc digital output 5 d6 33 adc digital output 6 d7 34 adc digital output 7 d8 35 adc digital output 8 d9 36 adc digital output 9 (msb) oe 37 output enable control input (low: outputs active; high: outputs in high impedance) v ccd2 38 digital supply 2 dgnd2 39 digital ground 2 clk 40 data clock input
2002 oct 25 6 philips semiconductors product speci?cation 10-bit, 3.0 v, up to 18 msps analog-to-digital interface for ccd cameras tda8787a agnd3 41 analog ground 3 v cca3 42 analog supply 3 agnd5 43 analog ground 5 dclpc 44 regulator decoupling pin opga 45 pga output (test pin) opgac 46 pga complementary output (test pin) shp 47 preset sample-and-hold pulse input shd 48 data sample-and-hold pulse input symbol pin description 1 2 3 4 5 6 7 8 9 10 11 36 35 34 33 32 31 30 29 28 27 26 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 12 24 37 25 tda8787ahl fce331 d9 d8 d7 d6 d4 d3 d2 d1 d0 ognd v cco v ccd3 dgnd3 agnd4 in agnd1 v cca1 cpcds2 ofdout blk clpdm d5 shp opgac opga dclpc agnd5 v cca3 clk dgnd2 oe v ccd2 shd agnd3 cpcds1 stdby test1 test2 test3 agnd2 v cca2 v ccd1 dgnd1 sclk sen vsync clpob sdata fig.2 pin configuration.
2002 oct 25 7 philips semiconductors product speci?cation 10-bit, 3.0 v, up to 18 msps analog-to-digital interface for ccd cameras tda8787a limiting values in accordance with the absolute maximum rating system (iec 60134). note 1. the supply voltages v cca , v ccd and v cco may have any value between - 0.3 and +5.0 v provided that the supply voltage difference d v cc remains as indicated. handling inputs and outputs are protected against electrostatic discharges in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. thermal characteristics symbol parameter conditions min. max. unit v cca analog supply voltage note 1 - 0.3 +5.0 v v ccd digital supply voltage note 1 - 0.3 +5.0 v v cco output stages supply voltage note 1 - 0.3 +5.0 v d v cc supply voltage difference between v cca and v ccd - 0.5 +0.5 v between v cca and v cco - 0.5 +1.2 v between v ccd and v cco - 0.5 +1.2 v v i input voltage referenced to agnd - 0.3 +5.0 v i o data output current - 10 ma t stg storage temperature - 55 +150 c t amb ambient temperature - 20 +75 c t j junction temperature - 150 c symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 76 k/w
2002 oct 25 8 philips semiconductors product speci?cation 10-bit, 3.0 v, up to 18 msps analog-to-digital interface for ccd cameras tda8787a characteristics v cca =v ccd = 3.0 v; v cco = 2.6 v; f pix = 18 mhz; t amb = - 20 to +75 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v cca analog supply voltage 2.7 3.0 3.6 v v ccd digital supply voltage 2.7 3.0 3.6 v v cco digital outputs stages supply voltage 2.5 2.6 3.6 v i cca analog supply current all clamps active - 50 60 ma i ccd digital supply current - 13 17 ma i cco digital outputs supply current c l = 20 pf on all data outputs; input ramp response time is 800 m s - 12ma p tot total power consumption v cca =v ccd =v cco =3v - 190 - mw v cca =v ccd =v cco = 2.7 v - 170 - mw digital inputs i nputs : pins stdby, clpdm, clpob, sclk, sdata, sen, vsync, oe, clk and blk v il low-level input voltage 0 - 0.6 v v ih high-level input voltage 2.2 - 5.0 v i i input current 0 v i v ccd - 2 - +2 m a i nputs : pins shp and shd v il low-level input voltage 0 - 0.6 v v ih high-level input voltage 2.2 - 5.0 v i i input current 0 v i v ccd - 10 - +10 m a clamps g lobal characteristics of the clamp loops t w(clamp) clamp active pulse width in numbers of pixels pga input code = 255 for maximum 4 lsb error 12 -- pixels i nput clamp : pin clpdm g m(cds) cds input clamp transconductance 1.5 2.7 3.5 ms o ptical black clamp : pin clpob g shift gain from cpcds1 and 2 to pga inputs - 0.27 - i lsb(cp) charge pump current for 1 lsb error at adc output pga input code = 0 - 20 -m a pga input code = 383 - 0.60 -m a
2002 oct 25 9 philips semiconductors product speci?cation 10-bit, 3.0 v, up to 18 msps analog-to-digital interface for ccd cameras tda8787a correlated double sampling (cds): pin in v i(cds)(p-p) cds input amplitude (video signal) (peak-to-peak value) v cc = 2.85 v 650 -- mv v cc 3 3.0 v 800 -- mv v i(rst)(max) maximum cds input reset pulse amplitude 500 -- mv i i input current at ?oating gate level - 1 - +1 m a c i input capacitance - 2 - pf t cds(min) cds control pulses minimum active time v i(cds)(p-p) = 800 mv; black-to-white transition in 1 pixel ( 2 lsb typical); t amb =25 c; note 1 11 15 - ns t h(in-shp) hold time shp to in t amb =25 c; see figs 3 and 4 - 12ns t h(in-shd) hold time shd to in t amb =25 c; see figs 3 and 4 - 12ns ampli?er dr pga pga dynamic range - 36 - db d g pga pga gain step - 0.3 - +0.3 db analog-to-digital converter (adc) le (i) integral non-linearity error f pix = 18 mhz; ramp input - 1.3 2.5 lsb le (d) differential non-linearity error f pix = 18 mhz; ramp input - 0.5 0.9 lsb total chain characteristics (cds, pga and adc) f pix(max) maximum pixel frequency 18 -- mhz f pix(min) minimum pixel frequency 2 -- mhz t clkh clock high time 15 -- ns t clkl clock low time 15 -- ns t d(shd-clk) time delay shd to clk see fig.3 10 -- ns t su(blk-clk) set-up time of blk compared to clk 10 -- ns v i(in) video input dynamic signal for adc full-scale output pga input code = 0 800 -- mv pga input code = 383 12.7 -- mv n tot(rms) total noise from cds input to adc output (rms value) see fig.8 pga input code = 0 - 0.15 - lsb pga input code = 96 - 0.8 - lsb v n(i)(eq)(rms) equivalent input noise voltage (rms value) pga input code = 383 - 70 -m v pga input code = 0 - 120 -m v o ccd(max) maximum offset between ccd ?oating level and ccd dark pixel level - 80 - +80 mv symbol parameter conditions min. typ. max. unit
2002 oct 25 10 philips semiconductors product speci?cation 10-bit, 3.0 v, up to 18 msps analog-to-digital interface for ccd cameras tda8787a note 1. depending on application environments and especially in case of high gain operation and digital supply with jitter, it is preferable to apply 12 ns or higher cds pulses. digital-to-analog converter (ofdout dac) v ofdout(p-p) additional 8-bit control dac (ofd) output voltage (peak-to-peak value) r l =1m w- 1.0 - v v ofdout dc output voltage ofd input code 0 - agnd - v ofd input code 255 - agnd + 1.0 - v tc ofd ofd output range temperature coef?cient - 250 - ppm/k z ofdout ofd output impedance - 2000 -w i ofdout ofd output drive current static -- 100 m a digital outputs (f pix = 18 mhz; c l =10pf) ; see figs 3 and 4 v oh high-level output voltage i oh = - 1ma v cco - 0.5 - v cco v v ol low-level output voltage i ol =1ma 0 - 0.5 v i oz off-state output current 0. 5v 2002 oct 25 11 philips semiconductors product speci?cation 10-bit, 3.0 v, up to 18 msps analog-to-digital interface for ccd cameras tda8787a handbook, full pagewidth n 0.6 v 0.6 v 2.2 v n + 1n + 2n + 3 t cds(min) t clkh t h(in-shp) 0.6 v 0.6 v 0.6 v 0.6 v 0.6 v t h(in-shd) 0.6 v 2.2 v 2.2 v t cds(min) t d(shd-clk) t su(blk-clk) 2.2 v fce337 in shp shd clk data blk t h(o) t d(o) n - 1 n 50% fig.3 pixel frequency timing diagram with active high-level polarities.
2002 oct 25 12 philips semiconductors product speci?cation 10-bit, 3.0 v, up to 18 msps analog-to-digital interface for ccd cameras tda8787a handbook, full pagewidth n 0.6 v 0.6 v 2.2 v n + 1n + 2n + 3 t clkl t h(in-shp) 2.2 v 2.2 v 2.2 v 2.2 v t h(in-shd) 0.6 v 2.2 v 0.6 v t cds(min) t cds(min) t d(shd-clk) t su(blk-clk) 0.6 v 0.6 v fce328 in shp shd clk data blk t h(o) t d(o) n - 1 n 50% fig.4 pixel frequency timing diagram with active low-level polarities.
2002 oct 25 13 philips semiconductors product speci?cation 10-bit, 3.0 v, up to 18 msps analog-to-digital interface for ccd cameras tda8787a handbook, full pagewidth fce332 0 v ofdout (v) 1.0 0 255 ofd control dac input code fig.5 dac output voltage output as a function of dac input code. handbook, full pagewidth fce333 blk (active high) clpob (active high) pga output 4 pixels (1) video optical black clpob window horizontal flyback dummy video blk window fig.6 line frequency timing diagram. (1) in this case the number of clamp pixels is limited to 18 (t w(clamp) ); otherwise this timing interval can be
2002 oct 25 14 philips semiconductors product speci?cation 10-bit, 3.0 v, up to 18 msps analog-to-digital interface for ccd cameras tda8787a 0 64 192 320 pga input code 128 total gain (db) 256 383 42 30 6 0 12 24 36 18 fce327 adc input range is 1 v pp . fig.7 total gain as a function of pga input code. handbook, halfpage fce329 n tot(rms) (lsb) 5 4 3 2 0 6 1 0 64 192 320 pga input code 128 256 383 noise measurement at adc outputs; coupling capacitor at input is grounded, so only noise contribution of the front-end is evaluated. front-end works at 18 mpixels with line of 1024 pixels whose first 40 are used to run clpob and the last 40 for clpdm. data at the adc outputs are measured during the other pixels. as a result of this, the standard deviation of the codes statistic is computed, resulting in the noise. fig.8 typical total noise performance as a function of pga gain.
2002 oct 25 15 philips semiconductors product speci?cation 10-bit, 3.0 v, up to 18 msps analog-to-digital interface for ccd cameras tda8787a handbook, full pagewidth ofdout dac latches pga gain latches adc clamp latches control pulse polarity latches latch selection sd0 lsb msb s data sclk sen 8-bit dac fce334 pga control adc clamp control control pulses polarity settings vsync sd1 sd2 sd3 sd4 sd5 10 sd6 shift register sd7 sd8 sd9 a0 a1 8 9 7 6 flip-flop flip-flop flip-flop fig.9 serial interface block diagram. handbook, full pagewidth fce335 sdata sclk sen a1 a0 sd9 sd7 sd6 sd5 sd4 sd3 msb lsb sd2 sd1 sd0 t hd3 t su3 t su1 t hd4 t su2 sd8 fig.10 loading sequence of control input data via the serial interface. t su1 =t su2 =t su3 = 10 ns (minimum); t hd3 =t hd4 = 10 ns (minimum).
2002 oct 25 16 philips semiconductors product speci?cation 10-bit, 3.0 v, up to 18 msps analog-to-digital interface for ccd cameras tda8787a table 1 serial interface programming; see figs 9 and 10 table 2 polarity settings note 1. bit sd4 is not used. table 3 standby mode selection; pin stdby table 4 output enable ( oe) pin 37 address bits data bits sd9 to sd0 a1 a0 0 0 pga gain control (bits sd8 to sd0); bit sd9 should be set to logic 0 0 1 dac ofdout output control (bits sd7 to sd0); bits sd8 and sd9 should be set to logic 0 1 0 adc clamp reference control (sd6 to sd0); from code 0 to 127; bits sd7, sd8 and sd9 should be set to logic 0 1 1 control pulses polarity settings (pins shp, shd, clpdm, clpob, blk and clk) symbol pin serial control bit (1) active edge or level shp and shd 47 and 48 sd0 1 = high; 0 = low clk 40 sd1 1 = high; 0 = low clpdm 12 (connected to ground) sd2 always 0 = low clpob 13 sd3 1 = high; 0 = low blk 11 sd5 1 = high; 0 = low vsync 24 sd6 0 = rising; 1 = falling stdby adc digital outputs; pins d9 to d0 i cca +i cco +i ccd (typical) 1 logic state low 1.5 ma 0 active 64 ma oe adc digital outputs; pins d9 to d0 0 active, binary 1 high impedance
2002 oct 25 17 philips semiconductors product speci?cation 10-bit, 3.0 v, up to 18 msps analog-to-digital interface for ccd cameras tda8787a application information power and grounding recommendations when designing a printed-circuit board for applications such as pc cameras, surveillance cameras, camcorders and digital still cameras, care should be taken to minimize the noise. for the front-end integrated circuit, the basic rules of printed-circuit board design and implementation of analog components (such as additional operational ampli?ers) must be respected, particularly with respect to power and ground connections. the following additional recommendation is given for the cds input pin(s) which is /are internally connected to the programmable gain ampli?er. the connections between the ccd interface and cds input should be as short as possible and a ground ring protection around these connections can be beneficial. separate analog and digital supplies provide the best solution. if this is not possible to do this on the board then the analog supply pins must be decoupled effectively from the digital supply pins. if the same power supply and ground are used for all the pins then the decoupling capacitors must be placed as close as possible to the ic package. in order to minimize the noise due to package and die parasitics in a two-ground system, the following measures must be implemented: all the analog and digital supply pins must be decoupled to the analog ground plane. only the ground pin associated with the digital outputs must be connected to the digital ground plane. all the other ground pins should be connected to the analog ground plane. the analog and digital ground planes must be connected together at one point as close as possible to the ground pin associated with the digital outputs. the digital output pins and their associated lines should be shielded by the digital ground plane which can then be used as a return path for digital signals.
2002 oct 25 18 philips semiconductors product speci?cation 10-bit, 3.0 v, up to 18 msps analog-to-digital interface for ccd cameras tda8787a application diagram handbook, full pagewidth fce336 1 2 3 4 5 6 7 8 9 10 11 36 48 (2) (2) 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 35 34 33 32 31 30 29 28 27 26 12 25 tda8787ahl d9 d8 d7 d6 d4 d3 d2 d1 d0 ognd v cco v ccd3 dgnd3 agnd4 in agnd1 v cca1 cpcds2 ofdout blk clpdm d5 shp opgac opga dclpc agnd5 v cca3 clk dgnd2 oe v ccd2 shd agnd3 cpcds1 stdby test1 test2 test3 agnd2 v cca2 v ccd1 dgnd1 sclk sen vsync clpob sdata serial interface v cca v ccd ccd (2) v ccd v ccd v ccd v cca 100 nf v ccd 100 nf v ccd 100 nf 100 nf 100 nf v cca 100 nf 1 m f 1 m f 1 m f 1 m f 1 m f (1) fig.11 application diagram. (1) pins sen and vsync should be interconnected when no vertical synchronization signal is available, while control pin vsync should be programmed by serial interface as low-level active. (2) the timing of the signals on pins in, shd and shp has to comply with the hold times t h(in-shp) and t h(in-shd) (see fig.3).
2002 oct 25 19 philips semiconductors product speci?cation 10-bit, 3.0 v, up to 18 msps analog-to-digital interface for ccd cameras tda8787a package outline unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.60 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 99-12-27 00-01-19 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 q a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
2002 oct 25 20 philips semiconductors product speci?cation 10-bit, 3.0 v, up to 18 msps analog-to-digital interface for ccd cameras tda8787a soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2002 oct 25 21 philips semiconductors product speci?cation 10-bit, 3.0 v, up to 18 msps analog-to-digital interface for ccd cameras tda8787a suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 5. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. wave soldering is suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package (1) soldering method wave reflow (2) bga, lbga, lfbga, sqfp, tfbga, vfbga not suitable suitable hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable (3) suitable plcc (4) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (4)(5) suitable ssop, tssop, vso not recommended (6) suitable
2002 oct 25 22 philips semiconductors product speci?cation 10-bit, 3.0 v, up to 18 msps analog-to-digital interface for ccd cameras tda8787a data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2002 oct 25 23 philips semiconductors product speci?cation 10-bit, 3.0 v, up to 18 msps analog-to-digital interface for ccd cameras tda8787a notes
? koninklijke philips electronics n.v. 2002 sca74 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 753504/04/pp 24 date of release: 2002 oct 25 document order number: 9397 750 10096

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